Show HN: First Silicon, real chip bugs that AI models miss

First Silicon is a benchmark of 86 engineer fixes in open-source chip designs (84 real bugs, 70 from OpenTitan) in which models write SystemVerilog assertions judged by Yosys and SymbiYosys on both buggy and fixed versions. The best configuration, Claude Opus 5.5 at maximum effort, caught 16 of 86 cases with zero false alarms, and 67 of the 84 genuine fixes were caught cleanly by none of the four models at default settings. Letting Opus 5.5 call the bounded model checker did not close the gap, as the model dropped or changed 79% of counterexampled assertions, including 8 that had correctly exposed a bug.