Meet qwenGPU: Qwen3.5-2B With 45 Compiled GPU Layers That Run CUDA
qwenGPU is an experimental MIT-licensed project by developer Vixhal that compiles a 4-lane SIMT GPU into 45 untrained layers placed in front of Qwen3.5-2B's own 24 layers, using the model's Gated DeltaNet state as registers, program ROM and global memory. The host compiles CUDA to PTX with clang and feeds it to the model as tokens, and the model writes each launch itself; the developer reports every launch was exact, a reference interpreter matched an NVIDIA Tesla T4 on 49 of 49 kernels, and text drift is a KL of about 7e-4. Reported speed is about 10 to 15 tokens per second on Apple MPS, and no prebuilt checkpoint is published.