Helion adds compile-time heuristic kernel configuration selection
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PyTorch's Helion DSL adds a set of compile-time heuristics: at compile time it reads the kernel's IR and data flow, classifies the kernel as matmul, reduction, or pointwise, and directly generates configurations such as block size, num_warps, and num_stages, eliminating the need for autotuning. PyTorch says this achieves performance close to tuned results. This set of heuristics has been merged into Helion and is enabled by default on H100 and B200 using the Triton backend. If the ranges of the kernel's dimensions cannot all be determined at compile time, the heuristics do not trigger, and Helion falls back to the original default configuration. The related evaluations were all conducted on NVIDIA hardware.
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- PyTorch BlogFast by Default: Compile-Time Heuristics for Helion Kernels
Helion now uses compile-time heuristics that analyze a kernel's IR and dataflow to classify it as matmul, reduction, or pointwise and emit block sizes, warps, and stages without autotuning. On H100, the computed configs reach 1.18x hand-written FLA Triton for linear attention, 1.27x vLLM's handwritten CUDA reduction kernels, and 1.09x torch.compile max-autotune on a general reduction suite. The heuristics are merged into Helion and enabled by default on H100 and B200 with the Triton backend.
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